• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    The invention relates to a method for determining programming parameters for programming a resistive random access memory from an insulating state to a conductive state, said method comprising the following steps: - determination of the retention curves representing the increase of the resistance in the conductive state as a function of time for a given programming temperature and a given current limit; determination of a fault time in retention for each of the retention curves; determination of the curves representing the reduction of the fault time in retention as a function of the programming temperature for a given current limitation; for a given programming temperature, determination, from the curves representing the decrease of the fault time in retention, of a current limiting value to be applied to the resistive random access memory in order to obtain a fault time in the target retention .
    公开号:FR3021151A1
    申请号:FR1454346
    申请日:2014-05-15
    公开日:2015-11-20
    发明作者:Thomas Cabout；Elisa Vianello
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of non-volatile rewritable memories, and more specifically to resistive random access memories of the OxRRAM and CBRAM type. A resistive random access memory comprises first and second electrodes separated by a layer of electrically insulating material, and switches from an insulating state to a conductive state by applying a threshold voltage VSET between the first and second electrodes. BACKGROUND OF THE INVENTION Depending on the intended applications and performance, different types of memories are used. Thus, the SRAM type memories, or static random access memory, offer ultra-fast write times, required for example during calculations by a microprocessor. The major disadvantage of these memories is that they are volatile and that the size of the relatively large memory point does not allow to obtain a large storage capacity in a reasonable volume. DRAM type memories, or dynamic random access memory, performing the storage of electrical charges in capacities, offer a large storage capacity. These memories, however, have higher write times (a few tens of nanoseconds) than those of the SRAM type memories and are also volatile, the information retention time being of the order of a few tens of milliseconds. Conversely, for applications that require storage of the information even when the voltage is cut off, there are also solid state memory devices that retain the information in the absence of power: these devices are called nonvolatile memories. Thus, for many years, different technological solutions have been developed, and have led to the availability of non-volatile memories that can be written and erased electrically. For example: EPROMs ("Erasable Programmable Read Only Memories" in English, or erasable and programmable read only memories), whose content can be written electrically, but which must be subjected to UV radiation to erase the stored information; EEPROMs ("Electrically Erasable Programmable ROMs"), the content of which can be written and electrically erased, but which require, for their realization, semiconductor surfaces larger than the memories EPROM type, and are therefore more expensive to achieve. Since both of the above mentioned solutions have limitations in their application, manufacturers have been looking for ideal nonvolatile memory, which would combine the following features: write and erase, high density and low cost per bit, access random, short write and read times, good endurance, but also low power consumption and low power supply.
    [0002] There are also nonvolatile memories, called Flash memories, which do not have the drawbacks of the EPROMs or EEPROMs mentioned above. Indeed, a flash memory is formed of a plurality of memory cells can be individually electrically programmed, a large number of cells, called block, sector or page, can be erased simultaneously and electrically. Flash memories combine both the advantage of EPROM memories in terms of integration density and the advantage of EEPROMs in terms of electrical erasure. In addition, the durability and low power consumption of Flash memories make them interesting for many applications: digital cameras, cell phones, printers, personal assistants, laptops, portable reading and sound recording devices, USB sticks etc. In addition, Flash memories do not have mechanical elements, which gives them a fairly high resistance to shocks. In the era of "all-digital", these products have greatly expanded, allowing an explosion of the Flash memory market.
    [0003] Most nonvolatile commercial Flash memories use charge storage as the information coding principle. In practice, a charge trapping layer (usually polysilicon, or a dielectric such as SiN) is encapsulated between two dielectrics in the gate stack of a MOS transistor. The presence or absence of charge in this medium modifies the conduction of the MOS transistor and makes it possible to code the state of the memory. More recently, other types of non-volatile rewritable memories have appeared to reduce the voltages and programming times of Flash memories; there may be mentioned ferroelectric memories (FeRAM memories or "Ferroelectric RAM"), based on the switching of the polarization, or magnetic memories (MRAM or "Magnetic RAM" memories) that use the direction of the remnant magnetic field in the active material. However, the memories FeRAM and MRAM have difficulties that limit their downscaling. In order to overcome these difficulties, variable resistance memories (called RRAMs or "Resistive RAMs") are known; these are today the subject of great attention. The resistive type memories may have at least two states "off" or "on" corresponding to the transition from a resistive state ("HRS" state) to a less resistive state ("LRS" state)). RAMs with variable resistance are today the subject of great attention, in particular because of their low power consumption and their high operating speed. Binary data 0 or 1 are stored in a Metal / Isolating / Metal (MIM) structure having two distinct resistance states. FIG. 1 represents the structure of a memory cell RRAM 1 of the MIM type. This device 30 1 is formed by a stack comprising an active storage area 2 disposed between a conductive lower electrode 3 and a conductive upper electrode 4.
    [0004] Thus, the resistive type of memory cell can reversibly switch from a highly resistive state "HRS" ("High Resistance State"), also called "OFF" state, to a weakly resistive state "LRS" ("Low Resistance State"). ") Or" ON "state. It can therefore be used to store binary information. The write mechanism is called SET in the RRAM framework and consists of changing from the HRS state to the LRS state. To erase the information, the active material is switched from the LRS state to the HRS state, the erasure mechanism being called RESET. The LRS and HRS states are both drivers (with of course a better conduction of the LRS state compared to the HRS state); in the initial state, the active material of the active storage area 2 is insulating (PRS state, "Pristine Resistance State"). A first electrical stress must therefore be applied to the blank memory cell in order to generate the LRS state for the first time. The associated process, called FORMING, consists of a partially reversible breakdown of the active material, that is to say that after the transition from the insulating state PRS to the conductive state LRS, the resistance of the conducting state can be switched to the HRS state with a lower electrical stress (RESET operation). The phenomenon of resistance change is observed in different types of materials, suggesting different mechanisms of operation. We can thus distinguish several types of resistive memories. The field of the present invention relates more particularly to two categories of resistive memories: the memories comprising an active zone based on an active oxide-based material (OxRRAM memory or "RRAM oxide") such as a binary oxide of a transition metal; the memories comprising an active zone based on an ionically conductive material (CBRAM memories or "Conductive Bridging RAM") forming an ionic solid electrolyte disposed between an electrode forming an inert cathode and an electrode comprising a portion of ionizable metal, c that is to say a portion of metal that can easily form metal ions, and forming an anode.
    [0005] The operation of the CBRAM memories is based on the formation, within the solid electrolyte, of one or more metal filaments (also called "dendrites") between its two electrodes when these electrodes are brought to appropriate potentials. The formation of the filament makes it possible to obtain a given electrical conduction between the two electrodes. By modifying the potentials applied to the electrodes, it is possible to modify the distribution of the filament, and thus to modify the electrical conduction between the two electrodes. For example, by reversing the potential between the electrodes, it is possible to remove or reduce the metal filament, so as to remove or greatly reduce the electrical conduction due to the presence of the filament. In the "HRS" state, the metal ions from the ionizable metal portion of the soluble electrode are dispersed throughout the solid electrolyte. Thus, no electrical contact is established between the cathode and the anode, that is to say between the upper electrode and the lower electrode. The solid electrolyte comprises an electrically insulating zone of high resistivity between the anode and the cathode. When a positive VSET potential is applied to the anode, a redox reaction takes place at that electrode, creating mobile ions. The ions then move in the electrolyte under the effect of the electric field applied to the electrodes. Arrived at the inert electrode (the cathode), the ions are reduced, causing the growth of a metallic filament. The filament preferably grows in the direction of the soluble electrode. The memory then goes into the "LRS" state when the filament allows contact between the electrodes, making the stack conductive. This phase constitutes the "SET" of the memory. To go to the "RESET" state of the memory, a negative VRESET voltage is applied to the anode, causing the conductive filament to dissolve. As for the OxRRAM memories, as for the CBRAM memories, the filament model enjoys a broad consensus. It is therefore also based on the formation and breaking of one or more conduction paths (conductive filaments) in the oxide matrix, connecting the two electrodes. Formation and rupture of the conductive filaments are attributed to the presence of oxygen vacancies.
    [0006] It is important to note that in the case of OxRRAMs as in the case of CBRAMs, the SET operation makes it possible to pass the memory cell from a high resistance state HRS to a low resistance state LRS. As mentioned above, the SET is made by applying a sufficient VSET voltage across the memory element. The transition between the high and low resistance state (close to an oxide breakdown in the case of an OxRRAM memory) is very fast and results in a sudden increase in the current when the VSET voltage is reached. This increase is illustrated in Figure 2. This sudden increase in current is not self-limiting. If nothing is done to control this increase the current will increase to very high values likely to cause a very significant increase in temperature and destruction of the memory device. It is therefore necessary to limit by a compliance the increase of the current up to a certain value in order to obtain a low resistance state while keeping an integrated memory device. This limited current is called indifferently current limitation or adjustment current ("compliance" in English). The current limitation required during the write operation can be achieved by various means such as a resistor or a transistor in series with the memory: the addition of a resistor or a transistor in series makes it possible to limit the current passing throughout the memory point and resistance / transistor series. The use of a resistor R (illustrated in FIG. 3) placed in series with the memory element (here an OxRRAM memory) makes it possible to limit the current. The presence of the series resistor limits the current flowing throughout once the OxRRAM cell is switched to the low resistance state. At the beginning of the write operation (SET), the OxRRAM is in a high resistance state (HRS). Thus most of the applied voltage VApp between the resistor and the series memory is found at the terminals of the memory element (i.e. the voltage VR across the resistor is negligible compared to the voltage Vox across the memory). When the voltage across the OxRRAM memory becomes sufficient (i.e. higher than the VSET threshold voltage) the switching occurs (switching from HRS mode to LRS mode) and the current increases rapidly. The voltage across the series R resistor increases to "cash" the excess voltage. This reduction in the voltage across the memory cell therefore limits the increase in current in the memory. The use of a series transistor (illustrated in FIG. 4) is very close to the use of the resistor R in series. In the same way, when writing the current increase causes an increase in the voltage across the transistor in series. The advantage of using a transistor with respect to a series resistor is to be able to control the level of limitation by means of the gate voltage. The higher the gate voltage, the higher the saturation current will be. The transistor thus serves as a means of adjusting the current limitation in the OxRRAM memory. One development path for the OxRRAM and CBRAM memories is the retention of information, that is, the retention of the "HRS" state and the "LRS" state. It seeks to improve the stability of insulating and conductive states over time. It has been shown that the current limitation used during the SET write operation has a strong influence on the information retention performance. Thus, in the article "Improvement of data retention in Hf02 / Hf 1T1R RRAM cell under low operating current" (Chen YY et al - IEEE 2013), it is shown that the current limitation during the SET write operation has a significant influence on retention performance: current limitation degrades retention performance. In other words, a memory cell written with a current limitation IC1 has better retention stability than when written with a current limitation IC2 less than IC1. Decreasing the current limitation during the write operation produces LRS states with higher resistance and lower stability (i.e., faster increase in resistance and hence lower information). This phenomenon is illustrated in FIG. 5 which represents the evolution of the current at a given voltage of 0.1V crossing a memory cell once written in an LRS state as a function of time, this evolution being obtained with two different current limitations: 40kLA and 10Pa. This evolution therefore represents the evolution of the resistance of the LRS state as a function of time. The cell written with a limitation of 40pA has a better stability than the one written with a limitation of 10pA (all the other experimental conditions being equal) and the initial resistance of SET with a limitation of 40pA is greater than the initial resistance of SET with a limitation of 10pA. The retention performance of the LRS state therefore depends on the current limitation and therefore the level of the LRS resistance at the time of writing.
    [0007] It has also been shown (see article "Temperature impact (up to 200 ° C) on the performance and reliability of Hf02 -based RRAMs" (Cabout T. et al.- IEEE 2013)) that the programming temperature of the memory (ie the temperature at which the memory is located when the SET or RESET operation is performed) has very little effect on the resistance levels of the LRS and HRS states of these memories. The curves in FIG. 6 represent the evolution of the initial resistances in the LRS (bottom curve) and HRS (top curve) state as a function of the programming temperature applied (respectively at the time of the SET and RESET operations). . These curves show that the temperature has virtually no influence on the resistance levels. The resistance of the LRS state is thus the same regardless of the writing temperature. Note that it is the same for the resistance of the HRS state. SUMMARY OF THE INVENTION In this context, the invention aims in particular to provide a method for determining programming parameters for programming a resistive random access memory of the OxRRAM or CBRAM type offering improved retention stability. To this end, a first aspect of the invention therefore relates to a method for determining programming parameters for programming a resistive random access memory from an insulating state to a conductive state, said memory comprising first and second electrodes separated by a layer of electrically insulating material, and passing from the insulating state to the conductive state by applying a threshold voltage between the first and second electrodes, the current flowing in said memory after the transition from the insulating state to the conductive state being limited by current limiting means, said method comprising the following steps: determining the retention curves representing the increase of the resistance in the conductive state as a function of time, each retention curve being determined for a temperature given programming and a current limitation; determining a fault time in retention for each of said retention curves; determining the curves representing the decrease of the fault time in retention as a function of the programming temperature, each curve being determined for a given current limitation; for at least one given programming temperature, determination, from said curves representing the decrease of the retention fault time as a function of the programming temperature, of the current limiting value to be applied to said resistive random access memory in order to obtain a fault time in target retention.
    [0008] The present invention results from the surprising finding, described in detail later, that the programming temperature to which the resistive random access memory is subjected at the time of its writing (ie SET operation for passing the memory from its highly resistive state HRS to its low resistive state LRS) has a significant influence on retention performance. Thus, a high temperature programming write will provide degraded performance in retention compared to a write made at a lower programming temperature. This observation is all the more surprising since, as mentioned above, the level of resistance of the memory at the time of writing does not depend on the programming temperature, while the performance in retention depends on this level of resistance. On the basis of the observation that certain applications (particularly in the automobile industry) need to maintain satisfactory retention performance regardless of the programming temperature, the method according to the invention makes it possible to compensate for any deterioration in retention performance due to an increase in the programming temperature by choosing a suitable current limiting value to provide this compensation. By fault time in target retention is meant a fault time determined from a predetermined criterion; in the initial state (t = 0), that is to say immediately after having applied the write operation, the resistance RoN of the memory in the "LRS" state is minimal. Then, over time, the resistance in the "LRS" state increases. The predetermined criterion consists for example in defining a resistance threshold beyond which it is considered that the retention of information is no longer ensured. This threshold resistance is reached after a certain retention time which will be identified as the fault time in retention. From this threshold, we consider that the memory is in a state of failure. For example, and without limitation, consider that the information in the memory cell is lost when its resistance has increased by a factor of 2 compared to its initial resistance RoN just after programming (t = 0). In addition to the features which have just been mentioned in the preceding paragraph, the method according to a first aspect of the invention may have one or more additional characteristics among the following, taken individually or in any technically possible combination: according to a first variant , the method according to the invention comprises a step of measuring the programming temperature before the write operation allowing the resistive random access memory to go from an insulating state to a conductive state, a current limiting value being determined for each measured programming temperature so as to obtain a substantially constant target retention fault time regardless of the value of the measured temperature in a given temperature range; According to a second variant, the programming temperature varies within a given temperature range, the method comprising a step of determining a single current limiting value corresponding to the upper limit of the given temperature range so as to obtain a target retention fault time at said upper bound, said unique limiting value also being applied to said resistive RAM for lower temperatures within said given temperature range; the determination of the retention curves representing the increase of the resistance in the conductive state as a function of time for a given programming temperature and a given current limitation is carried out by experimental measurements obtained on one or more resistive RAMs presenting characteristics identical to the resistive random access memory to be programmed; according to one embodiment, said resistive RAM to be programmed is an OxRRAM type memory; according to another embodiment, said resistive random access memory to be programmed is a CBRAM type memory; the method according to the invention may comprise a step of determining, for said target retention fault time, a plurality of pairs of programming temperature values associated with a current limitation; in this case, the method may also comprise a step of determining a curve representing the increase of the current limitation as a function of the programming temperature. The present invention also relates to a computer program product comprising means for implementing a method according to the invention.
    [0009] The invention and its various applications will be better understood by reading the following description and examining the figures that accompany it. BRIEF DESCRIPTION OF THE FIGURES The figures are presented for information only and in no way limitative of the invention. FIG. 1 schematically illustrates a memory device of the OxRRAM or CBRAM type; FIG. 2 illustrates the abrupt transition from the high resistance state to the low resistance state during the write operation of an OxRRAM or CBRAM type memory device; FIG. 3 schematically illustrates the limitation of current flowing through an OxRRAM memory by the use of a series resistor; FIG. 4 schematically illustrates the limitation of current flowing through an OxRRAM memory by the use of a series transistor; Figure 5 shows the evolution of the current in an OxRRAM memory once written as a function of time for two different current limitations; FIG. 6 represents the evolution of the initial resistances in the LRS and HRS state as a function of the programming temperature applied; FIG. 7 represents the evolution of the resistance of an OxRRAM memory in the LRS state as a function of time for different programming conditions; FIG. 8 illustrates the various steps of the programming method according to the invention; FIG. 9 represents the evolution of the resistance of an OxRRAM memory in the LRS state as a function of time for different programming conditions as well as the determination of the fault time in retention; Figure 10 shows the evolution of fault time in retention as a function of the programming temperature for different current limitations; Figure 11 shows the evolution of the current limitation as a function of the programming temperature for a given target retention time. DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT OF THE INVENTION Unless otherwise specified, the same element appearing in different figures has a unique reference.
    [0010] The method according to the invention will be described in greater detail in what follows in the case of an OxRRAM (or "RRAM Oxide") memory comprising an active zone based on an oxide-based active material such as a binary oxide. a transition metal M (Mx0y) surrounded by two metal electrodes (see Figure 1). It is therefore a MOM (Metal-Oxide-Metal) structure based on the change in resistance of the oxide layer which passes from a highly resistive state HRS to a low resistive state LRS when a voltage is applied. sufficient VSET writing across the electrodes and that goes from a low resistive LRS state to a low resistive HRS state when a sufficient VRESET write voltage is applied across the electrodes. There is a large number of binary oxides having the ability to change resistance reversibly. These memories can be bipolar (VSET and VRESET voltages of opposite sign) or unipolar (VSET and VRESET of the same sign); they can also work in some cases in both modes (bipolar and unipolar). The OxRRAM memory presented below is a TiNfTi / Hf02 / TiN type memory (hence an upper electrode formed of a TiN / Ti bilayer, an active HfO2 oxide storage region and a TiN lower electrode). that this example is given purely by way of illustration and not limitation, the method according to the invention being capable of being applied to any type of OxRRAM memory (for example a TiN / Hf / HfO 2 / TiN structure or a Ti / HfO 2 / structure TiN or a structure Pt / TiO2 / Pt). The method according to the invention also applies to CBRAM type memories having a solid electrolyte disposed between an electrode forming an inert cathode and an electrode comprising a portion of ionizable metal (versus OxRRAM type memories whose metal electrodes are chosen for be slightly ionizable). An example of CBRAM memory is for example formed by a stack comprising a solid electrolyte, for example based on doped chalcogenide (eg GeS) or oxide (eg A1203) disposed between a lower electrode, for example Pt, forming an inert cathode, and an upper electrode having a portion of ionizable metal, for example copper, forming an anode.
    [0011] As mentioned above, the present invention is based on the observation that, even if the programming temperature has no effect on the resistance of the LRS state, it modifies the stability of this state (and therefore the retention performance of the state). 'information). Thus, after writing at high temperature, the retention performance is degraded. As for certain applications (for example in the automotive field) high temperature writing is essential, the invention aims to provide a method for maintaining the retention performance constant or at least greater than a given threshold, regardless of the temperature programming.
    [0012] The phenomenon underlying the programming method according to the invention is illustrated in FIG. 7 which shows, for a TiN / Ti / HfO 2 / TiN type OxRRAM memory, the retention of the "LRS" state represented by the evolution of the resistance of the memory in this state, as a function of time. FIG. 7 gives four examples of "LRS" state retention curves C1, C2, C3 and C4 each obtained with different initial programming conditions (initial condition pair including a current limiting value and a value of programming temperature): The curve C1 is obtained with a current limitation of 7011A and a programming temperature of 150 ° C; Curve C2 is obtained with a current limitation of 70 μL and a programming temperature of 25 ° C; curve C3 is obtained with a current limitation of 35011A and a programming temperature of 150 ° C; Curve C4 is obtained with a current limitation of 350pA and a programming temperature of 25 ° C. In general, regardless of the curve C1, C2, C3 or C4, in the initial state (t = 0), that is to say immediately after forming the conductive filament, the resistance RoN of the memory to the state "LRS" is minimal. Then, over time, the resistance in the "LRS" state increases. In this FIG. 7, the logarithmic curves show the retention curves for two current limitations (70pA and 350pA) and for two programming temperatures (25 ° C and 150 ° C). In other words, starting from the same sample memory, at t = 0, the latter is passed from an HRS state to an LRS state with four pairs of different programming conditions; the programming conditions are: the programming temperature at which the memory is written; the current limitation (compliance) applied to it. For the record, it is necessary to limit by a compliance the increase of the current up to a certain value in order to obtain a low resistance state while keeping an integrated memory device (to avoid a definite breakdown of the oxide). The current limitation required during the write operation is carried out by current limiting means in the memory consisting, for example, of using a transistor in series with the memory (see FIG. 4): the current limitation is then adjustable via the control of the gate voltage of the transistor. Once written (i.e. once the transition to the LRS state ensured), the memory is then placed at a given temperature (called retention temperature) and the evolution of the resistance as a function of time is measured. Note that the retention temperature (here equal to 250 ° C) may be different from the programming temperature. A retention temperature higher than the operating temperature of the memory provided by the industrial specifications is often used in order to be able to observe a lack of retention * of the information more quickly. In accordance with the state of the art mentioned above, FIG. 7 shows that the LRS states written with a low current limitation (ie 70 1.1A) are less stable (curves C1 and C2 in dashed lines) and have a higher initial resistance. 25 important. In addition, also in accordance with the state of the art, it is observed that the writing temperature has no influence on the value of the initial resistance (curves C1 and C2 obtained respectively at 150 ° C. and 25 ° C. C for the same limitation of 70pA have the same resistance value at the initial moment, likewise the curves C3 and C4 obtained respectively at 150 ° C and 25 ° C for the same limitation of 350pA have the same resistance value at the initial moment). 302 1 1 5 1 16 On the other hand, it is observed that even if the initial states have the same resistance, the stability is degraded when the cell is programmed at high programming temperature (150 ° C.). In other words, the memory according to the curve C1 loses the information faster than the memory according to the curve C2 (with the same current limitation and an identical initial resistance value) and the memory according to the curve C3 loses more quickly the information that memory according to curve C4. It can therefore be seen that high temperature programming makes retention lose stability while increasing the limiting current makes it gain. The programming method according to the invention takes advantage of the above finding to determine a current limitation adapted to control the retention performance. The various steps of the method 100 according to the invention are illustrated in FIG. 8. The first step 101 of the method according to the invention will consist in determining retention curves representing the increase of the resistance in the conductive state LRS according to time, each retention curve being determined for a given programming temperature and a given current limitation; the set of curves is preferably obtained with the same retention temperature Retention higher than the operating temperature of the memory provided by the industrial specifications to be able to observe a lack of retention of information more quickly. The four curves C1 to C4 of Figure 7 are examples of such curves. Figure 9 also shows four retention curves Si, S2, S3 and S4 to illustrate generally the method according to the invention. The curve S1 is obtained with a current limitation equal to IC2 and a programming temperature of Tset2 (150 ° C); curve S2 is obtained with a current limitation equal to IC2 and a Tset1 programming temperature (25 ° C); curve S3 is obtained with a current limitation equal to IC1 and a programming temperature of Tset2 (150 ° C); curve S4 is obtained with a current limitation equal to ICI and a programming temperature of Tset1 (25 ° C). As mentioned above, it is observed that the current limitation ICI strictly greater than the current limitation IC2 makes it possible to compensate for the loss of retention stability when using the programming temperature Tset2 strictly greater than the programming temperature Tset1. Of course, the method according to the invention requires obtaining a plurality of curves corresponding to many different pairs (IC, Tset), the only curves S1 to S4 being given here for purely illustrative purposes. Step 101 is performed experimentally using one or more reference OxRRAM memories; in the case where several memories are used, it will be necessary to choose reference memories having the same characteristics in terms of materials and structure. The programming method according to the invention will then be used to program memories of the same type as the memory or memories on which the experimental measurements were made. The second step 102 of the method according to the invention will then consist in determining a fault time in retention for each of the retention curves; to do this, it is appropriate to choose a criterion for obtaining a fault time. This criterion is an arbitrary criterion and the invention is absolutely not limited to a particular criterion. In the following we will use the criterion of an increase of the initial resistance (resistance of SET at t = 0s) by a factor of 2. Thus, it is considered that the information in the memory is lost when its resistance has increased. a factor of 2 in relation to its initial resistance just after its programming (at t = 0s). Thus, for each curve 51, S2, S3 and S4, the fault times in retention are retrieved (ie the time required for the resistance to change from a value R (t = 0) to a value R (t = 0) x2). Four fault times tfail1, tfail2, tfail3 and tfail4 respectively correspond to the curves S1, S2, S3 and S4 and therefore to the programming conditions (IC2, Tset2), (IC2, Tset1), (IC1, Tset2) and (IC1, Tset1).
    [0013] According to step 103 of the programming method according to the invention, the fault retention times determined during the previous step 102 will be used to place them on a curve representing the evolution of the fault time in retention as a function of the programming temperature for different current limitations. FIG. 10 thus represents a plurality of curves representing the evolution of the fault time in retention as a function of the programming temperature for different current limitations; by way of example, the curve W1 corresponds to the evolution of the fault time in retention as a function of the programming temperature for a current limitation IC1; similarly, the curve W2 corresponds to the evolution of the fault time in retention as a function of the programming temperature for a current limitation IC2, the curve W3 corresponds to the evolution of the fault time in retention as a function of the temperature for programming a current limitation IC3 and the curve Wref corresponds to the evolution of the fault time in retention as a function of the programming temperature for a reference current limitation ICreference. As mentioned above, it is generally observed (i.e. regardless of the current limiting value) a reduction of the fault time in retention when the programming temperature increases. It is also observed that the curve W1 is above the curve W2 which is itself above the curve W3 which is itself above the curve Wref: this arrangement is explained by the fact that the current ICI is greater than the current IC2 which is itself greater than the current IC3 itself higher than the current ICreference. The specifications for using memories of the OxRRAM or CBRAM type vary according to the fields of application and are more or less restrictive. Thus, the specifications may require that the memories operate with a certain retention time over a given temperature range: by way of illustration, a retention of 1 to 3 years can be required over a range of 0 ° C. to 40 ° C. 30 memories intended for mass consumption or a larger retention (of the order of 15 years) in the automotive field with a very wide range in temperature (for example -40 ° C to 150 ° C).
    [0014] Therefore, according to a first embodiment, if the user wants to have the same stability in retention for one or more given writing temperatures (for example Tprogi - Pro and Tg2i 1, the programming method according to the invention will include a step 104 consisting of drawing a horizontal line on the curves of FIG. 10 corresponding to the target retention fault time (t-standard) that it wishes to obtain (for example for a reference programming temperature and the current limitation ICreferenoe) and to draw a vertical line corresponding to each writing temperature considered (here Tp T rogl - - Prog2) - The intersection of these two lines gives the desired operating point to obtain the same performance in retention (ie the same fault time in retention regardless of the programming temperature of the temperature range specified by the specifications). to use the current limitation corresponding to the curve passing on this point. Here for the two programming temperatures Tprogi and Tprog2 the two programming currents Here and Ic2 corresponding to the two operating points P1 and P2 are respectively obtained. All of these operating points can then be used to represent the evolution of the current limitation as a function of the programming temperature for the same given target retention time. This curve is illustrated in FIG. 11. The implementation of this first embodiment therefore involves measuring the temperature of the memory to be programmed; as a function of the measured temperature and knowing the target retention time, the limiting current to be applied to the memory is deduced therefrom; this current limitation is for example set via the gate of a transistor in series with said memory. According to this embodiment, the device integrating the memory or memories to be programmed is equipped with temperature measuring means for providing a measurement of the temperature at the time of programming the memory or memories and thus to determine the operating point ( ie the current limitation associated with the programming temperature) to obtain the desired target retention time. According to an alternative to the first embodiment, the user can decide to have a satisfactory stability in retention (and not necessarily identical) for one or more given writing temperatures; to do this, the programming method according to the invention will comprise a step 104 'of choosing the maximum temperature of the temperature range covered by the specifications and then determining, from the curves of Figure 10, the current limitation to apply, to obtain a desired retention time; this current limitation thus determined will be applied to the memory over the entire temperature range; in other words, the current limitation will be "over-sized" so as to have a desired retention time in the maximum programming temperature condition; for illustrative purposes, in the range [Trèference - Tprog21, to obtain a fault time in target retention (tfad_standard), one sets at the temperature TProg2; it is deduced the current limitation Ic2 to apply. This current limitation Ic2 will be applied to the memory regardless of the temperature in the range [Reference - Tprog2].
    权利要求:
    Claims (9)
    [0001]
    REVENDICATIONS1. A method of determining programming parameters for programming a resistive random access memory from an insulating state to a conductive state, said memory comprising first and second electrodes separated by a layer of electrically insulating material, and passing from the insulating state to the conductive state by applying a threshold voltage between the first and second electrodes, the current flowing in said memory after the transition from the insulating state to the conductive state being limited by current limiting means, said method comprising the following steps: determination of the retention curves representing the increase of the resistance in the conductive state as a function of time, each retention curve being determined for a given programming temperature and a given current limitation; determining a fault time in retention for each of said retention curves; determining the curves representing the decrease of the fault time in retention as a function of the programming temperature, each curve being determined for a given current limitation; for at least one given programming temperature, determination, from said curves representing the decrease of the retention fault time as a function of the programming temperature, of a current limiting value to be applied to said resistive random access memory in order to get a fault time in target retention.
    [0002]
    2. Method according to claim 1 characterized in that it comprises a step of measuring the programming temperature before the write operation allowing the resistive random access memory to go from an insulating state to a conductive state, a value current limiting circuit being determined for each measured programming temperature so as to obtain a substantially constant target retention fault time irrespective of the value of the measured temperature in a given temperature range.
    [0003]
    3. Method according to claim 1 characterized in that the programming temperature varies within a given temperature range, the method comprising a step of determining a single current limiting value corresponding to the upper limit of the given temperature range. so as to obtain a target retention fault time at said upper bound, said single limiting value also being applied to said resistive RAM for lower temperatures within said given temperature range.
    [0004]
    4. Method according to one of the preceding claims characterized in that the determination of the retention curves representing the increase of the resistance in the conductive state as a function of time for a given programming temperature and a given current limitation is achieved. by experimental measurements obtained on one or more resistive RAMs having identical characteristics to the resistive random access memory to be programmed.
    [0005]
    5. Method according to one of the preceding claims characterized in that it comprises a step of determining, for said target retention fault time, a plurality of programming temperature value pair associated with a current limitation.
    [0006]
    6. Method according to the preceding claim characterized in that it comprises a step of determining a curve representing the increase of the current limitation as a function of the programming temperature.
    [0007]
    7. Use of the method according to one of the preceding claims for programming an OxRRAM type memory.
    [0008]
    8. Use of the method according to one of claims 1 to 6programming a CBRAM type memory.
    [0009]
    A computer program product comprising program code means for performing the steps of the method according to any one of claims 1 to 6 when said program is running on a computer.
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    法律状态:
    2015-04-22| PLFP| Fee payment|Year of fee payment: 2 |
    2015-11-20| PLSC| Search report ready|Effective date: 20151120 |
    2016-04-27| PLFP| Fee payment|Year of fee payment: 3 |
    2017-04-21| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1454346A|FR3021151B1|2014-05-15|2014-05-15|METHOD FOR DETERMINING PROGRAMMING PARAMETERS FOR PROGRAMMING RESISTIVE LIVER MEMORY|FR1454346A| FR3021151B1|2014-05-15|2014-05-15|METHOD FOR DETERMINING PROGRAMMING PARAMETERS FOR PROGRAMMING RESISTIVE LIVER MEMORY|
    EP15167406.6A| EP2945161B1|2014-05-15|2015-05-12|Method for determining programming parameters for programming a resistive random-access memory|
    US14/713,127| US9263129B2|2014-05-15|2015-05-15|Method for determining programming parameters for programming a resistive random access memory|
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